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1 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity april 2000 2000 integrated device technology, inc. dsc-5413/- c idt74lvc16901a extended commercial temperature range 1 clkenab 2 clkenab leab oeab odd/even 1 a 1 - 1 a 8 sel b-port parity generate and check a data 2 a-port parity generate and check b data 18-bit storage clkab 1 apar 1 errb 2 a 1 - 2 a 8 2 apar 2 errb 1 b 1 - 1 b 8 1 bpar 1 erra 2 b 1 - 2 a 8 2 bpar 2 erra oeba clkba 1 clkenba 2 clkenba leba 18-bit storage 18 18 18 18 q a q b 2 2 1 32 3 30 5 61 28 36 34 31 63 64 33 62 29 37 35 60 4 features: ?typical t sk(0) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? 0.50mm pitch tssop package ? extended commercial range of -40c to +85c ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4w typ. static) ? all inputs, outputs and i/o are 5 volt tolerant ? supports hot insertion drive features for lvc16901: ? high output drivers: 24ma ? reduced system switching noise applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems 3.3v cmos 18-bit universal bus transceiver with par- ity generators/checkers, 5v tolerant i/o no no no no no t recommended t recommended t recommended t recommended t recommended for new designs for new designs for new designs for new designs for new designs functional block diagram description: this 18-bit universal bus transceiver is built using advanced dual metal cmos technology. the lvc16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. the device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. the lvc16901 features independent clock (clkab or clkba), latch- enable (leab or leba), and dual 9-bit clock enable ( clkenab or clkenba ) inputs. it also provides parity-enable ( sel ) and parity-select (odd/ even ) inputs and separate error-signal ( erra and errb ) outputs for checking parity. the direction of data flow is controlled by oeab and oeba . when sel is low, the parity functions are enabled. when sel is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. inputs can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvc16901 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance.
2 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity 1998 integrated device technology, inc. dsc-123456 c tssop top view pin configuration 1 clkenab leab clkab 1 erra v cc gnd 1 a 1 v cc so64-1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 56 57 58 59 60 61 62 63 64 1 v cc gnd v cc gnd gnd 25 26 27 28 40 39 38 37 2 bpar clkba 2 clkenab sel 29 30 31 32 36 35 34 33 2 clkenba 1 apar gnd 1 clkenba leba 1 errb 1 bpar gnd 1 a 2 1 a 3 1 a 4 1 a 5 1 a 6 1 b 1 1 b 2 1 b 3 1 b 4 1 b 5 1 b 6 1 a 7 1 a 8 2 a 1 1 b 7 1 b 8 2 b 1 2 a 2 2 b 2 2 a 3 2 b 3 gnd gnd 2 b 4 2 b 5 2 a 4 2 a 5 2 a 6 2 a 8 2 a 7 2 b 6 2 b 7 2 b 8 oeab 2 erra 2 apar odd/even 2 errb oeba pin description pin names description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input xclkenab a-to-b 9-bit clock enables xclkenba b-to-a 9-bit clock enables clkab a-to-b clock input clkba b-to-a clock input xerra a error-signal outputs xerrb b error-signal outputs xapar a port parities xbpar b port parities odd/ even parity select input sel parity enables xax a-to-b data inputs or b-to-a 3-state outputs xbx b-to-a data inputs or a-to-b 3-state outputs capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 6.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf lvc link note: 1. as applicable to the device type. absolute maximum ratings (1) symbol description max. unit v term terminal voltage with respect to gnd ? 0.5 to +6.5 v t stg storage temperature ? 65 to +150 c i out dc output current ? 50 to +50 ma i ik i ok continuous clamp current, v i < 0 or v o < 0 ? 50 ma i cc i ss continuous current through each v cc or gnd 100 ma lvc link note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
3 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity function table (1,2) parity enable inputs outputs clkenab oeab leab clkab xax xbx xhxx xz xlhx ll xlhxhh hllx x b 0 (3) lll ll lll hh llllx b 0 (3) lllhx b 0 (4) notes: 1. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, and clkenba . 2. h = high voltage level l = low voltage level x = don?t care z = high-impedance = low-to-high transition 3. output level before the indicated steady-state input conditions were established. 4. output level before the indicated steady-state input conditions were established, provided that clkab was low before leab went low. parity notes: 1. parity output is set to the level so that the specific bus side is set to even parity. 2. parity output is set to the level so that the specific bus side is set to odd parity. inputs operation or function sel oeba oeab lhl parity is checked on port a and is generated on port b. llh parity is checked on port b and is generated on port a. lhh parity is checked on port b and port a. lll parity is generated on port a and b if device is in ff mode. hll parity functions are q a data to b, q b data to a hlh disabled; device acts as q b data to a hhl a standard 18 bit registered q a data to b hhh transceiver. isolation inputs outputs sel oeba oeab odd/even of inputs a1 ? a8 = h of inputs b1 ? b8 = h xapar xbpar xapar xerra xbpar xerrb l h l l 0, 2, 4, 6, 8 n/a l n/a n/a h l z l h l l 1, 3, 5, 7 n/a l n/a n/a l h z l h l l 0, 2, 4, 6, 8 n/a h n/a n/a l l z l h l l 1, 3, 5, 7 n/a h n/a n/a h h z l l h l n/a 0, 2, 4, 6, 8 n/a l l z n/a h l l h l n/a 1, 3, 5, 7 n/a l h z n/a l l l h l n/a 0, 2, 4, 6, 8 n/a h l z n/a l l l h l n/a 1, 3, 5, 7 n/a h h z n/a h l h l h 0, 2, 4, 6, 8 n/a l n/a n/a l h z l h l h 1, 3, 5, 7 n/a l n/a n/a h l z l h l h 0, 2, 4, 6, 8 n/a h n/a n/a h h z l h l h 1, 3, 5, 7 n/a h n/a n/a l l z l l h h n/a 0, 2, 4, 6, 8 n/a l h z n/a l l l h h n/a 1, 3, 5, 7 n/a l l z n/a h l l h h n/a 0, 2, 4, 6, 8 n/a h h z n/a h l l h h n/a 1, 3, 5, 7 n/a h l z n/a l l h h l 0, 2, 4, 6, 8 0, 2, 4, 6, 8 l l n/a h n/a h l h h l 1, 3, 5, 7 1, 3, 5, 7 l l n/a l n/a l l h h l 0, 2, 4, 6, 8 0, 2, 4, 6, 8 h h n/a l n/a l l h h l 1, 3, 5, 7 1, 3, 5, 7 h h n/a h n/a h l h h h 0, 2, 4, 6, 8 0, 2, 4, 6, 8 l l n/a l n/a l l h h h 1, 3, 5, 7 1, 3, 5, 7 l l n/a h n/a h l h h h 0, 2, 4, 6, 8 0, 2, 4, 6, 8 h h n/a h n/a h l h h h 1, 3, 5, 7 1, 3, 5, 7 h h n/a l n/a l l l l l n/a n/a n/a n/a pe (1) z pe (1) z l l l h n/a n/a n/a n/a po (2) z po (2) z
4 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity operating characteristics, t a = 25 o c dc electrical characteristics over operating range following conditions apply un less otherwise specified: operating condition: t a = ?40 o c to +85 o c symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih i il input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5 a i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ? 18ma ? ? 0.7 ? 1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl i cch quiescent power supply current v cc = 3.6v v in = gnd or v cc ??10a i ccz 3.6 v in 5.5v (2) ??10 ? i cc quiescent power supply current variation one input at v cc - 0.6v other inputs at v cc or gnd ? ? 500 a lvc lin k notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3.0v 2.4 ? v cc = 3.0v i oh = ? 24ma 2.2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3.0v i ol = 24ma ? 0.55 lvc lin k note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = ? 40c to +85c. v cc = 1.8v v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf 37 52 68 pf c pd power dissipation capacitance outputs disabled f = 10mhz 16 22 28 pf
5 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity switching characteristics (1) (continued on next page) v cc = 1.8v (2) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. min. max. unit f max 125 ? 125 ? 125 ? 125 ? mhz t plh t phl propagation delay xax to xbx or xbx to xax ? 7 1 6.2 ? 5.8 1 5.4 ns t plh t phl propagation delay xax to xbpar or xbx to xapar ? 12.7 2 9.9 ? 8.6 2 7.7 ns t plh t phl propagation delay xapar to xbpar or xbpar to xapar ? 8.4 1 6.7 ? 6.2 1 5.7 ns t plh t phl propagation delay xapar to x erra or xbpar to x errb ? 13 2 10.7 ? 9.7 2 8.5 ns t plh t phl propagation delay odd/ even to x errb or x erra ? 9.9 1.5 9.7 ? 8.9 1.5 7.8 ns t plh t phl propagation delay odd/ even to xapar or xbpar ? 10.4 1.5 9.3 ? 8.6 1.5 7.5 ns t plh t phl propagation delay sel to xapar or xbpar ? 9.5 1 7.1 ? 6.9 1 6.1 ns t plh t phl propagation delay leba to xax or leab to xbx ? 9.5 1 7 ? 6.5 1 5.8 ns t plh t phl propagation delay leba to xapar or leab to xbpar (parity feed through) ? 11 1.5 7.7 ? 7 1.5 6.3 ns t plh t phl propagation delay leba to xapar or leab to xbpar (parity generated) ? 14.5 2.5 10.8 ? 9.3 2 8.4 ns t plh t phl propagation delay leba to x errb or leab to x erra ? 15.3 2.5 10.9 ? 9.5 2 8.5 ns t plh t phl propagation delay clkba to xax or clkab to xbx ? 10.5 1 7.4 ? 6.8 1 6.1 ns t plh t phl propagation delay clkba to xapar or clkab to xbpar (parity feed through) ? 11.5 1.5 8.1 ? 7.3 1.5 6.6 ns t plh t phl propagation delay clkba to xapar or clkab to xbpar (parity generated) ? 15.5 2.5 11.2 ? 9.7 2 8.7 ns t plh t phl propagation delay clkba to x errb or clkab to x erra ? 16.5 2.5 11.5 ? 9.9 2 8.9 ns
6 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity switching characteristics (continued) (1) v cc = 1.8v (2) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. min. max. unit t pzh t pzl output enable time oeab or oeba to xbx, xbpar or xax, xapar ? 8.4 1.4 7.3 ? 7.1 1 6.3 ns t pzh t pzl output enable time oeab or oeba to x erra or x errb ? 9 1.4 7.2 ? 6.5 1 5.9 ns t pzh t pzl output enable time sel to x erra or x errb ? 9.5 1.4 7.7 ? 7.5 1 6.5 ns t phz t plz output disable time oeab or oeba to xbx, xbpar or xax, xapar ? 8.1 1.3 7.1 ? 6.2 1.5 5.9 ns t phz t plz output disable time oeab or oeba to x erra or x errb ? 9.3 1.3 8.3 ? 7.5 1 6.7 ns t phz t plz output disable time sel to x erra or x errb ? 9.2 1.3 7.4 ? 6.4 1.5 5.9 ns t su set-up time, high or low, xax, xapar or xbx, xbpar before clk 4.7 ? 2.7 ? 2.8 ? 2.5 ? ns t su set-up time, high or low, x clkenab or x clkenba before clk 4.5 ? 2.9 ? 2.9 ? 2.5 ? ns t su set-up time, high or low, xax, xapar or xbx, xbpar before le 0 ? 2.2 ? 2.1 ? 2 ? ns t h hold time, high or low, xax, xapar or xbx, xbpar after clk 0 ? 1.2 ? 1.2 ? 1.3 ? ns t h hold time, high or low, x clkenab or x clkenba after clk 0 ? 1.3 ? 1.3 ? 1.5 ? ns t h hold time, high or low, xax, xapar or xbx, xbpar after le 1.7 ? 1.7 ? 1.9 ? 1.7 ? ns t w pulse width leab or leba high 3 ? 3 ? 3 ? 3 ? ns t w pulse width clkab or clkba high or low 4 ? 3 ? 3 ? 3 ? ns t sk (o) output skew (3) ? ? ? ? ? ? ? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. based on idt characterization. 3. skew between any two outputs of the same package and switching in the same direction.
7 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol+ v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v oh- v hz lvc link test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position output skew - tsk (x) pulse width symbol v cc (1) = 3.3v 0.3v v cc (1) = 2.7v v cc (2) = 2.5v 0.2v unit v load 662 x vccv v ih 2.7 2.7 vcc v v t 1.5 1.5 v cc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf lvc link test switch open drain disable low enable low v load disable high enable high gnd all other tests open lvc lin k definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. note: 1. diagram shown for input control enable-low and input control disable-high.
8 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity p arameter measurement informa tion vcc = 1.8v output control (low level enabling) t plz 0v output waveform 1 s1 at 2 x vcc (2) t pzh output waveform 1 s1 at open (2) t phz 0v v ol + 0.15 v v oh v cc /2 v cc /2 t pzl v cc v ol v oh ? 0.15 v v cc /2 v cc /2 v cc v cc /2 v cc /2 v cc 0v input t w v cc /2 v cc /2 v cc 0v data input v cc /2 v cc 0v timing input t su t h v cc 0v v cc /2 v cc /2 v cc /2 v cc /2 v oh v ol t phl t plh input output 2 x v cc open gnd 1 k ? 1 k ? s1 c l = 30pf (1) from output under test test s1 t pd open t plz /t pzl 2 x vcc t phz /t pzh gnd load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control . waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output contr ol. 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 ? , t r 2ns, t f 2ns. 4. the outputs are measured one at a tiime with one transition per measurement. 5. t plz and t phz are the same as t dis . 6. t pzl and t pzh are the same as t en . 7. t plh and t phl are the same as t pd .
9 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity p arameter measurement informa tion vcc = 2.5v 0.2v output control (low level enabling) t plz 0v output waveform 1 s1 at 2 x vcc (2) t pzh output waveform 1 s1 at gnd (2) t phz 0v v ol + 0.15 v v oh v cc /2 v cc /2 t pzl v cc v ol v oh ? 0.15 v v cc /2 v cc /2 v cc v cc /2 v cc /2 v cc 0v input t w v cc /2 v cc /2 v cc 0v data input v cc /2 v cc 0v timing input t su t h v cc 0v v cc /2 v cc /2 v cc /2 v cc /2 v oh v ol t phl t plh input output 2 x v cc open gnd 500 ? 500 ? s1 c l = 30pf (1) from output under test test s1 t pd open t plz /t pzl 2 x vcc t phz /t pzh gnd load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control . waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output contr ol. 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 ? , t r 2ns, t f 2ns. 4. the outputs are measured one at a tiime with one transition per measurement. 5. t plz and t phz are the same as t dis . 6. t pzl and t pzh are the same as t en . 7. t plh and t phl are the same as t pd .
10 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity p arameter measurement informa tion vcc = 2.7v and 3.3v 0.3v output control (low level enabling) t plz 0v output waveform 1 s1 at 6v (2) t pzh output waveform 1 s1 at gnd (2) t phz 0v v ol + 0.3 v v oh 1.5v 1.5v t pzl 3v v ol v oh ? 0.3 v 1.5v 1.5v 2.7v 1.5v 1.5v 2.7v 0v input t w 1.5v 1.5v 2.7v 0v data input 1.5v 2.7v 0v timing input t su t h 2.7v 0v 1.5v 1.5v 1.5v 1.5v v oh v ol t phl t plh input output 6 v open gnd 500 ? 500 ? s1 c l = 50pf (1) from output under test test s1 t pd open t plz /t pzl 2 x vcc t phz /t pzh gnd load circuit voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms enable and disable times voltage waveforms pulse duration notes: 1. c l includes probe and jig capacitance. 2. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control . waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output contr ol. 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 ? , t r 2ns, t f 2ns. 4. the outputs are measured one at a tiime with one transition per measurement. 5. t plz and t phz are the same as t dis . 6. t pzl and t pzh are the same as t en . 7. t plh and t phl are the same as t pd .
11 extended commercial temperature range idt74lvc16901a 3.3v cmos 18-bit universal bus transceiver with parity *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* idt xx lvc xxx xx package device type temp. range pa 16 74 thin shrink small outline package (so64-1) 18-bit universal bus transceiver with parity generators/ checker -40c to +85c xxxx family bus-hold 901 no bus-hold double-density with resistors, 24ma blank

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